1. Field of the Invention
The present invention relates to a semiconductor memory device, for example, a semiconductor memory device in which a ferroelectric material is used to form memory cells.
2. Description of the Related Art
A ferroelectric memory (ferroelectric random access memory: FeRAM) stores binary data in a nonvolatile fashion based on the fact that states of two charge amounts (polarization amounts) Q can be set when a voltage applied to a ferroelectric material is zero. The memory cell is configured by a ferroelectric capacitor having a ferroelectric film sandwiched between two electrodes.
In the conventional ferroelectric memory, one end of a circuit of a ferroelectric capacitor and cell transistor which are connected in parallel is connected to a plate line and the other end thereof is connected to a bit line. The potential of the bit line varies according to the polarization state of the ferroelectric capacitor by setting potentials of the word line and plate line to a high level. It is assumed that a case wherein the potential that is read onto the bit line after inversion of the polarization state corresponds to “1” data, for example, and a case wherein the potential that is read without inversion of the polarization state corresponds to “0” data, for example.
A potential read out onto the bit line is amplified to a low or high level by the sense amplifier in the case of “0” or “1” data, respectively. After this, if data held is “0”, data is rewritten by respectively applying high and low levels to one end and the other end of the ferroelectric capacitor. Therefore, the “0” rewriting operation is instantly terminated by holding the potential of the plate line at the high level and amplifying the potential of the bit line to the low level. In the case of “1” data, the rewriting operation is performed by respectively applying low and high levels to one end and the other end of the ferroelectric capacitor. The “1” rewriting operation can be attained by amplifying the potential of the bit line to the high level and setting the potential of the plate line to the low level.
Thus, it is necessary to set up two voltage application states in one read cycle in order to perform the rewriting operation for “0” data and “1” data. For this reason, it is difficult to reduce the read time.